1. Field of the Invention
This invention relates generally to charge transfer devices and, more particularly, is directed to an improved clocking signal drive circuit for the charge transfer devices.
2. Description of the Prior Art
Charge transfer devices (CTDs) are well-known in the prior art to include a plurality of capacitive storage elements each capable of capacitively holding a variable amount of charge. These capacitive storage elements are arranged in a series and connected so that, under the influence of a clocking signal, the charge on one of the capacitive storage elements will be transferred to the successive capacitive storage elements in the series.
Two well-known types of CTDs are the bucket brigade device (BBD) and the charge coupled device (CCD). A BBD is comprised of a series of capacitors, each having two plates, a series connected plate and a clocking plate. The series connected plate of each capacitor is connected to the series connected plate of the preceding capacitor by a transfer transistor. The clocking plate of each capacitor and the control electrode of each transfer transistor are each supplied with one of a plurality of clocking signals. An input signal voltage is applied across the first capacitor in the series of capacitors which places a voltage having a corresponding signal level on the first capacitor. The voltage of the clocking signals are then varied so that the transfer transistor between the first and the second capacitors is turned on. As a result, charge flows from the second capacitor, which is originally charged with a standard voltage level higher than the signal level to the first capacitor. This transfer continues until the voltage across the first capacitor is raised from the signal level to the standard level at which point the voltage at the series plate of the first capacitor equals the voltage of the clocking signal supplied to the base of the transfer transistor which causes the transfer transistor to be turned off. This transfer of charge causes the voltage across the second capacitor, which has the same capacitance as the first, to drop from a standard level to the signal level. This process is repeated under the control of the clocking signals, so that the signal level originally placed on the first capacitor is sequentially transferred from one capacitor to another, enabling the BBD to store or delay, for a desired length of time the signal applied to its first capacitor.
A CCD is comprised of a series of successive electrodes each of which is capacitively coupled with a common semi-conductor channel and each of which is supplied with one of a plurality of clocking signals. An input signal voltage is applied between the first electrode of this series and the common channel, and results in the presence of charge in the common channel which is capacitively coupled to the first electrode. Then, the clocking signals cause different voltages to be applied to the first and second electrodes of the CCD, such that the charge formerly coupled to the first electrode is attracted to the second electrode. Under the control of the clocking signals, this process is repeated with the charge originally placed on the first electrode being sequentially transferred from one electrode to another, so that the CCD can store or delay, for a desired length of time, the signal applied to its first electrode.
The above description of BBDs and CCDs indicates the importance therein of clocking signal drive circuits which supply clocking signals to the capacitive storage means of such CTDs. In the prior art, such clocking signal drive circuits are comprised of a clock generator which provides one or more clocking control signals having the desired frequency and phase information for the generation of one or more clocking signals, and one or more driver circuits, each of which receives one of the clocking control signals and acts as a current amplifier for that signal so that the clocking signal which it provides to the CTD will be capable of properly driving that device. The driver circuits used in the prior art are comprised of a pair of NPN transistors connected in series between a power supply and ground with a diode having its anode connected to the emitter of the more positive of the two transistors and its cathode connected to the collector of the more negative of the two transistors. The base of the more positive of the two transistors is connected to the positive power supply through a resistor and to the collector of a third NPN transistor. The base of the more negative of the two transistors is connected to ground through a resistor and to the emitter of the third transistor. The base of the third transistor is connected to the collector of a fourth NPN transistor having its emitter connected to the output of the clock generator and its base connected to the positive power supply through a resistor.
As will be described in greater detail below, the foregoing circuit has many problems associated with its operations. First of all, it requires four transistors and a diode for each driver circuit, which increases the cost of the charge transfer device and which also increases the current demands required by such a driver circuit. Furthermore, such a driver circuit operates with some of its output transistors in saturation. This increases the time it takes for the driver circuit to change the clocking signal which it produces between low and high voltage levels. This has the undesirable effect of reducing the frequency at which the CTD can operate. In addition such a driver circuit has a disadvantage in that it cannot be used as an output device for measuring the charge level on one or more of the capacitive elements contained within a CTD.
In prior art charge transfer devices the standard means for measuring the charge level on one of the capacitive storage element is to connect one of the electrodes of such capacitive storage element to the base of a transistor connected to operate as an emitter follower, so that the voltage at the emitter of the emitter follower transistor will vary as a function of the voltage on the electrode of the charge transfer device to which its base is connected.
Such means for measuring the signal within a charge transfer device has two major drawbacks, the first of which is that there is a considerable stray capacitance C.sub.CB between the collector and the base of the emitter follower transistor. This stray capacitance has the effect of making it appear that the capacitance of the capacitive storage element to which the base of the emitter follower transistor is connected is larger than the capacitance of all the other capacitors of the CTD by the amount of C.sub.CB. Such additional capacitance at the capacitive storage element to which the emitter follower transistor is connected destroys the uniform relationship which exists throughout the rest of the CTD between the voltage and the charge upon each of the capacitive storage elements. As a result, when charge flows from the capacitive storage element to which the emitter follower transistor is connected to its preceding capacitive storage element the decrease in the voltage of the discharging capacitive storage element will be less than the increase in voltage of the preceding capacitive storage element which is being charged. By reason of the foregoing, the final voltage across the capacitive storage element connected to the emitter follower transistor and the voltage at the emitter of such transistor will not accurately reflect the voltage which formerly was on the preceding capacitive storage element.
The use of an emitter follower transistor to measure the voltage on a capacitive storage element in a CTD gives rise to a further problem due to the base current in such a transistor. The base current drains charge from the capacitive storage element to which it is connected, thus decreasing the voltage across that capacitive storage element relative to what it should be, and thereby introducing an error in the output voltage measured at the emitter of the emitter follower transistor.
The use of emitter follower transistors to measure the voltage upon capacitive storage elements of a CTD has a further disadvantage when used with CTD which, as is well-known, are designed to function as filter circuits. At any given time, the charge level stored on every other capacitive storage element of a CTD is equal to a function of the charge level which was originally supplied to the input of the CTD at a time which varies for each such capacitive storage element according to the clocking frequency supplied to the charge transfer device and according to the sequential position of that capacitive storage element from the input of the CTD. By measuring the charge levels at a specified plurality of the capacitive storage elements, and by weighing the measured charge levels with a desired ratio and adding them together, it is possible to derive a value which varies as a function of the frequency of the input signal applied to the CTD. In such filter circuit according to the prior art, the charge level in each of the plurality of capacitive storage elements being sampled is determined by connecting the base of an emitter follower transistor with each such capacitive storage element while the emitter of each emitter follower transistor is connected to one input of a respective differential amplifier, which has its output connected to a device measuring the total amount of current flowing through all of the differential amplifiers.
Such a method of deriving the output from a filter circuit comprised of a CTD has many drawbacks. First of all, each of the emitter follower transistors connected to one of the capacitive storage elements of the CTD has an undesirable stray capacitance C.sub.CB and an undesirable base current, which not only decrease the accuracy of the measurement of the charge level on the respective capacitor, but also destroy the accuracy of that charge level as it is transferred onto successive capacitive storage element of the CTD. Further, the described prior art output circuit for a CTD filter circuit requires a large number of components, which increases the size, current requirements, and cost of the filter circuit. In addition, the prior art filter circuit has the undesirable feature of requiring that the current amplification of each its differential amplifiers be accurately fixed, which is quite difficult, particularly, in a filter circuit having many differential amplifiers.